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Next Generation Performance Monitoring

Title: Next Generation Performance Monitoring.
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Name(s): West, Paul E. (Paul Edwin), 1982-, author
Tyson, Gary, professor directing dissertation
Gerber, Larry, university representative
Whalley, David, committee member
Wang, Andy, committee member
Department of Computer Science, degree granting department
Florida State University, degree granting institution
Type of Resource: text
Genre: text
Issuance: monographic
Date Issued: 2010
Publisher: Florida State University
Place of Publication: Tallahassee, Florida
Physical Form: computer
Physical Form: online resource
Extent: 1 online resource
Language(s): English
Abstract/Description: As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no inter-core counters. In fact, performance counters were not originally designed to be exploited by users as they now are, but used simply as aids for hardware debugging and testing during system creation. As such, they tend to be an "afterthought" in the design, with no standardization across or within platforms. Nonetheless, given access to these counters, researchers are using them to great advantage. Furthermore, evaluating counters for multicore systems has become a complex and resource-consuming task. This dissertation explores a Performance Monitoring System consisting of a specialized CPU core designed to allow efficient collection and evaluation of performance data for both static and dynamic optimizations. A synthesizable hardware implementation is created and compared to modern day processors. Furthermore, each component and the ISA of the system is thoroughly explored. This system provides a transparent mechanism to dynamically change how architectural features inform the operating system of process behavior, and assist in profiling and debugging. For instance, a piece of hardware watching snoop packets can determine when a write-update cache coherence protocol would be helpful or detrimental to the currently running program. The Performance Monitoring System is designed to let the hardware feed performance statistics back to the software, allowing dynamic architectural adjustments at runtime. SPLASH2 benchmarks are evaluated for cache coherency policy and task scheduling. Using these two examples, this dissertation shows how the Performance Monitoring System is programmed to find performance improvements. A 16% average performance improvement was found for cache coherency and 17% improvement was found for task scheduling.
Identifier: FSU_migr_etd-1150 (IID)
Submitted Note: A Dissertation Submitted to the Department of Computer Science in Partial FulfiLlment of the Requirements for the Degree of Doctor of Philosophy.
Degree Awarded: Summer Semester, 2010.
Date of Defense: June 18, 2010.
Keywords: Performance Monitoring, Computer Architecture, Computer Science, Event Based, Processor Design
Bibliography Note: Includes bibliographical references.
Advisory committee: Gary Tyson, Professor Directing Dissertation; Larry Gerber, University Representative; David Whalley, Committee Member; Andy Wang, Committee Member.
Subject(s): Computer science
Persistent Link to This Record: http://purl.flvc.org/fsu/fd/FSU_migr_etd-1150
Owner Institution: FSU

Choose the citation style.
West, P. E. (P. E. ). (2010). Next Generation Performance Monitoring. Retrieved from http://purl.flvc.org/fsu/fd/FSU_migr_etd-1150